The ZL30274 is a feature-rich jitter attenuator with DPLLs and five extremely low output jitter synthesizers. This device is ideal for frequency conversion, jitter attenuation and frequency synthesis in a wide variety of equipment types requiring low jitter (<150fs) and multiple frequency families
Other devices in this family include ZL30731, ZL30732, ZL30733, ZL30734, ZL30631, ZL30632, ZL30633, ZL30634, ZL30635, ZL30641, ZL30642, ZL30643, ZL30644, ZL30645 and ZL30640 which are targeted for 5G SyncE and IEEE1588 timing card and line card applications.
Product Features
Additional Features
Any-to-any frequency conversion per channel
Inputs: up to 6, differential or singled-ended
Outputs: up to 10 differential, up to 20 CMOS
Output jitter <150fs RMS 156.25MHz 12k-20M
Core power consumption <0.9W
Input Clocks
Any input frequency from 1kHz to 1250MHz
Per-input activity and frequency monitoring
Automatic or manual reference switching
Revertive or nonrevertive switching
Any input can be a 0.5Hz to 8kHz Sync input for Ref+Sync frequency/phase/time locking
Input phase measurement, 1ps resolution
Per-input phase adjustment, 1ps resolution DPLLs
2 DPLL Channels
Hitless reference switching
Per-DPLL phase adjustment, 1ps resolution
Programmable bandwidth, tracking range, phase-slope limiting and other advanced features
Locking to gapped-clock input signals
Output Clocks
Any frequency 0.5Hz to 750MHz