Processor PC8548E

FEATURES • Embedded e500 Core, Initial Offerings up to 1.2 GHz – Dual Dispatch Superscalar, 7-stage Pipeline Design with out-of-order Issue and Execution – 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1) • 36-bit Physical Addressing • Enhanced Hardware and Software Debug Support • Double-precision Embedded Scalar and Vector Floating-point APUs • Memory Management Unit (MMU) • Integrated L1/L2 Cache – L1 Cache-32 KB Data and 32 KB Instruction Cache with Line-locking Support – L2 Cache-512 KB (8-Way Set Associative); 512 KB/256 KB/128 KB/64 KB Can Be Used As SRAM – L1 and L2 Hardware Coherency – L2 Configurable As SRAM, Cache and I/O Transactions Can Be Stashed Into L2 Cache Regions • Integrated DDR Memory Controller With Full ECC Support, Supporting: – 200 MHz Clock Rate (400 MHz Data Rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM • Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption Algorithms • Four On-chip Triple-speed Ethernet Controllers (GMACs) Supporting 10- and 100-Mbps, and 1-Gbps Ethernet/IEEE*802.3 Networks with MII, RMII, GMII, RGMII, RTBI and TBI Physical Interfaces – TCP/IP Checksum Acceleration – Advanced QoS Features • General-purpose I/O (GPIO) • Serial RapidIO and PCI Express High-speed Interconnect Interfaces, Supporting – Single x8 PCI Express, or Single x4 PCI Express and Single 4x Serial RapidIO • On-chip Network (OCeaN) Switch Fabric • Multiple PCI Interface Support – 64-bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O) – 64-bit PCI-X Bus Controller (Up to 133 MHz, 3.3V I/O), or Flexibility to Configure Two 32-bit PCI Controllers • 166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller