Thickness measuring system PWG™

geometryshapeflatness

The PWG™ patterned wafer metrology platform produces full wafer dense shape, comprehensive wafer flatness and dual-sided nanotopography data for advanced 3D NAND, DRAM and logic manufacturers. PWG5™, with high resolution and high-density sampling, measures stress-induced wafer shape changes, wafer shape-induced pattern overlay errors, wafer thickness variations and wafer front and backside topography. With industry-best dynamic range, the PWG5 supports inline monitoring and control of wafer warp and stress resulting from deposition processes used to fabricate the 96+ layer stacks of advanced 3D NAND devices. The PWG5 identifies process-induced wafer shape variations at the source, enabling re-work of the wafer, re-calibration of a process tool or integration with KLA’s 5D Analyzer® data analytics system to feed results to the scanner to improve on-product overlay and overall device yield. Applications Process monitoring, Inline monitoring, Lithography overlay control PWG5™ with XT Option Additional technologies extend the wafer handling and measurement capabilities of the PWG5 patterned wafer geometry system to support wafer-to-wafer bonding measurements for advanced wafer-level packaging applications. PWG3™ Third-generation patterned wafer geometry measurement system, supporting inline monitoring of fab-wide processes for a range of memory and logic device types at the 2X/1Xnm design nodes.